1. Field of the Invention
The present invention relates to a MOS type semiconductor integrated circuit device which achieves low power consumption by shutting down power supplied to a circuit while in a standby mode.
2. Description of the Related Art
Recently, in the semiconductor industry, with the growth of the market for a portable electronic device, there has been a demand for a semiconductor integrated circuit device intended to achieve low power consumption. The factors which determine power consumption of a semiconductor integrated circuit device may include: current consumption while in an active mode, i.e., during operation; and a leak current while in a standby mode being a cycle during which no operation is required. In addition, the leak current while in the standby mode in a semiconductor element such as a MOS transistor includes an off-leak current and a gate leak current.
FIG. 1 shows a configuration of a part of a conventional semiconductor integrated circuit device intended to achieve low power consumption. This circuit has: two CMOS inverter circuits 101 and 102 connected in series; and a switching P-channel MOS transistor 103 connected between a supply node of a power source voltage VDD and a common source at a P-channel MOS transistor side of the two CMOS inverter circuits 101 and 102. The switching transistor 103 is turned on while in an active mode, and is turned off while in a standby mode.
In the circuit of FIG. 1, the transistor 103 is turned off while in a standby mode, and power of the whole circuit is shut off, so that the off-leak current or gate leak current as described above are significantly reduced.
However, when the standby mode is switched to normal operation or vice versa, an unwanted penetration current flows between power supplies. In addition, the electric potential of each node becomes insufficient while in the standby mode, and thus, there is a danger that a malfunction occurs.
FIG. 2 shows a configuration of a part of another conventional semiconductor integrated circuit device intended to achieve low power consumption. This circuit has: two CMOS inverter circuits 101 and 102 connected in series; a switching N-channel MOS transistor 104 connected between a source at an N-channel MOS transistor side of one CMOS inverter circuit 101, and a supply node of a grounding voltage VSS; and a switching P-channel MOS transistor 105 connected to a source at a P-channel MOS transistor side of the other CMOS inverter circuit 102 and a supply node of a power source voltage VDD. The switching transistors 104 and 105 are turned on while in an active mode, and are turned off while in a standby mode.
In the circuit of FIG. 2, the transistors 104 and 105 are turned off while in a standby mode, and power source voltage of the whole circuit is shut off, so that reduction of the off-leak current as described above is achieved. Further, an occurrence of a malfunction caused by the shortage of an electric potential of each node can be prevented.
However, the power source voltage VDD is always supplied to the CMOS inverter circuit 101, so that a gate leak current flows while in a standby mode. That is, in the circuit of FIG. 2, reduction of the gate leak current while in the standby mode cannot be achieved.
In documents entitled “A 90 nm Low Power 32 K-Byte Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Application”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, pp. 247–250 (FIG. 4) and “16.7 fA/cell Tunnel-Leakage-Suppressed 16 Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors”, 2003 IEEE International Solid-State Circuits Conference (ISSCC 2003/Feb. 12, 2003/Salon 1-6/9:00 AM), respectively, a SRAM is described which is intended to reduce a leak current by reducing a value of a power source voltage while in a standby mode.